This invention relates to a method of making complementary metal oxide semiconductor (CMOS) device pairs and particularly to the steps in that method relating to the creation by doping of a pattern of adjacently arranged regions of opposing conductivity type in the insulatively supported semiconductor layer of these devices. The invention relates more particularly to the channel doping steps of that method.
In the pertinent CMSO technology, the method is applied to a composite wafer structure typically comprising a sapphire substrate on a major surface of which is formed a thin layer of semiconductor material, typically n type silicon. The CMOS circuitry made from the silicon-on-sapphire (SOS) structure is commonly referred to as CMOS/SOS. In a CMOS/SOS device pair, opposite conductivity type devices, referred to, individually, as n-channel and p-channel devices, are established in a single unit during essentially a single process. Near ideal isolation between devices is afforded by this technology, since the silicon between devices is removed, typically, by etching and each device is contained in an individual island on the sapphire substrate. This isolation, together with the small junction areas and minimum parasitic capacitance possible in an SOS technology, give promise of the realization of the ultimate density and speed potential of MOS circuits.
For either the n-channel or p-channel device, three functional regions, distinguished by the type and concentration of dopant present, are disposed in the silicon island. The first is a central or channel region of a first conductivity type which underlies an insulated conductive electrode commonly referred to as the gate. The other two functional regions are abutting or flanking regions of a second and opposite conductivity type which underlie and are in electrical contact with current path electrodes, one electrode together with its associated functional region commonly referred to as the source and other electrode together with its associated functional region commonly referred to as the drain. To minimize junction capacitance and thereby enhance the speed of the device, it is desirable to minimize the junction area at the interface between the functional regions. Ideally, this can be achieved by creating junction interfaces between doped regions which are at right angles to the plane of the silicon layer and to the edges of the device island.
The type and degree of conductivity in each of these regions is related to the type and relative concentration of impurity ions which are present. Either by design or because of the limitations of the doping technique which is used, these functional regions, typically, are not doped to a uniform impurity concentration from the upper to the lower surface of the silicon layer. For example, to provide a low resistance ohmic contact between the current path electrodes and the respective silicon regions, it is desirable to have impurity concentrations of approximately 10.sup.18 cm.sup.-3 or greater in the regions adjacent the upper surface of the silicon, whereas all or nearly all of the remainder of the region underlying the electrodes are doped to levels of approximately 10.sup.15 cm.sup.-3 The channel region is doped with impurity ions producing an opposite conductivity type, at concentrations of, typically, 10.sup.15 to 10.sup.16 cm.sup.-3.
Among the methods used to create the basic n-p-n and p-n-p conductivity configuration in the individual device islands, is the method where steps are taken first to create symmetrically in a conductivity sense, both entirely n and entirely p conductivity islands, in adjacent pairs, then subsequently, to subject these pairs to steps which counter-dope in a complementary pattern, the regions under the current path electrodes while retaining the precounter-doping conductivity characteristic in the channel region. Ideally, the depth and concentration of the impurities are dictated by design requirements. However, because of the limitations of specific doping techniques and constraints imposed on these techniques in consideration of other desirable features of such devices, such as radiation hardness, the dopant concentration profile has shortcomings which are manifested in the completed devices in terms of undesirable leakage currents, irregular shaped junction interfaces, and parasitic effects along the island edges.
To facilitate good circuit design, predictable device operating characteristics under anticipated environmental extremes is desirable. In particular, to provide reasonable design tolerances to the design of interfacing circuitry, variations in the CMOS device channel inversion voltage threshold should be minimized. It is known that exposure to high energy radiation environments comprising gamma rays, alpha particles, cosmic rays, and other highly energetic particles can induce large variations in the threshold voltage of CMOS/SOS devices where the devices have undergone high temperature processing for determinable time-at-temperature regimes.